You might instead consider basing your design on the M8093 Falcon SBC-11/21 and the T-11 processor? T-11's can be extracted from a variety of boards, such as versions of the RDRQ disk controller. http://archive.org/details/bitsavers_decpdp1111_15967429 http://archive.org/details/bitsavers_decpdp11t1_6963777 http://archive.org/details/bitsavers_decpdp11t1_7528719 http://simh.trailing-edge.com/semi/t11.html "The T-11 had the same feature set as the LSI-11 -- no floating point, no memory management -- but the integer performance of the F-11. It was implemented in a scaled version of the F-11 process -- 5u NMOS -- and operated at 250Mhz (400ns microcycle). The T-11 dissipated less than 1.2W and cost less than $10 in high volume." http://simh.trailing-edge.com/semi/f11.html http://simh.trailing-edge.com/semi/lsi11.html On Tue, Jul 30, 2013 at 7:24 AM, David Riley <fraveydank at gmail.com> wrote:

Holm Tiffe wrote: Just FYI: www.tiffe.de/Robotron/Bausteinuebersicht/K180x/1806BM2.pdf The datasheet of the N1806VM2, the 5Mhz 64Kbyte CMOS Version. The Text is russian, but all Signal Names are "normal letters" and there are some timing diagrams.. Regards, Holm -- Technik Service u. Handel Tiffe, www.tsht.de, Holm Tiffe, Freiberger Stra?e 42, 09600 Obersch?na, USt-Id: DE253710583 www.tsht.de, info at tsht.de, Fax +49 3731 74200, Mobil: 0172 8790 741

John Wilson wrote: I was born in east germany, therefore I had russian in the school (35 years before now), but this is almost all gone. I never had englisch in the school :-) I would do my very best to translate this and I do have a ukrainian Friend here in germany with his wife that was a teacher in russia so far as I know. I think both would help me. Next there is a friend, Oleg Safiulin As for the 1801/1806VM2 I can say at first that it has some additional select signals to address an console mode rom. The processor don't has the ODT in Microcode but in this (shadow)rom. (I have the contents from this rom). Mext detail is an adressless read after startup, the processor reads in some bits to determine the starting address of this console rom. The addressable memory is 64k for Console or system and 64k for the user. The consolee interface itself has to be the "normal" pdp11 circuit, they used Uarts like the 64S004 (but with additional -5V) for that. If I remember correctly the 1801VM2 ist the same as the 1806VM2 but the 2nd one is CMOS. The 1801 however is at least twice as fast as the 1806. It can be clocked with 20Mhz (Input) wich makes a system clock speed of 10Mhz. I do even have the internal schematics of that CPU, just in case you have some open questions.. *evil grin* Next I have some (poor quality) schematics of russian (home)computers using that CPU. Translation from russian wikipedia (http://ru.wikipedia.org/wiki/1801BMx) trough http://www.online-translator.com with some fixes from me: In comparison with K1801BM1, instructions of expanded arithmetics (MUL, DIV, ASH, ASHC - are part of a set of instructions of EIS), and also operations from a floating point (FIS command set) are added. The FIS instructions (FADD, FSUB, FMUL, FDIV) are realized trough subroutines - when performing these instructions there is a special type of interruption and the program handler in memory of the console mode is executed. (Trap?) Support of the multiprocessor configuration has been cleaned. This is for the 1801VM2, should also be correct for the 1806VM2. Regards, Holm -- Technik Service u. Handel Tiffe, www.tsht.de, Holm Tiffe, Freiberger Stra?e 42, 09600 Obersch?na, USt-Id: DE253710583 www.tsht.de, info at tsht.de, Fax +49 3731 74200, Mobil: 0172 8790 741

On 7/30/2013 8:45 AM, Holm Tiffe wrote: If you have some extra bucks one is for sale here in Minsk,Belarus http://www.ebay.com/itm/160922187015 450us OBO silly rate of shipping ($500 us) which pretty much would kill the deal. wonder if it glows? Jim

On 7/30/2013 11:47 AM, Alexandre Souza wrote: I'm confused, are you referring to the sale I found for the MK-90 or some other lot for $1000? $500 in the shipping pretty much violates us Ebay sales practice now days, they are banning people with outrageous shipping and handling costs if they feel like it. (have to qualify the statement as Ebay is pretty useless enforcing anything). I thought you were in Brazil, the sale I commented on was in Minsk. jim

Check

On Tue, Jul 30, 2013 at 10:17 AM, Kyle Owen <kylevowen at gmail.com> wrote: I thought originally you were trying to solve the problem of having an "extra" nibble to find room for, when using a 12-bit processor on an 8-bit bus. If that is called "extra", then having a 12-bit processor on a 16-bit bus has the opposite problem, which is a "missing" nibble.

On Tue, Jul 30, 2013 at 11:17 AM, Kyle Owen <kylevowen at gmail.com> wrote: Ignore it. Except that you might need to have some address range that is mapped as contiguous 8-bit bytes with the top 4 bits as don't care, so that you can deal with device registers without losing the ability to access half of the bits out of every other register.

On Tue, Jul 30, 2013 at 08:08:07PM +0100, Tony Duell wrote: There's definitely a user's manual for the J11, and I'm fairly sure I've seen one for the T11 (although IMHO it's too weird for daily use -- having to fake bus timeouts using a real interrupt is nasty). Using the 11/23 and/or 11/24 and/or PC325/350 prints to figure out the F11 is worth a shot, but I'd be worried about trying to do anything too different from what DEC did. There could be tons of stuff that's assumed in their designs, which would have to change, somehow, for an alien design. John Wilson D Bit

On Wed, Jul 31, 2013 at 02:40:32AM -0400, Paul Birkel wrote: I could have this entirely wrong, but there's stuff in RT-11 which puts NOPs after instructions that might cause bus timeouts, and my understanding is that it's because the T11 doesn't innately know about timeouts so the Falcon's Q-bus interface fakes them by doing a hardware interrupt through vector 4 (at prio=7 I assume?), which isn't guaranteed to take place before the next instruction fetch. Which means it breaks the usual autosize code: tst @#devcsr ;touch device (TST clears C) bcs 10$ ;isn't there ... ;is there (with vector 4 pointing at something like "bis #1,2(sp) / rti") ... which works on *every* other PDP-11 model. So it's annoying to have to special-case your code for this one CPU model, and it's not even some ancient kludge from the dark ages (which would be understandable), it's a fancy 1980s LSI chip made when they should have known better. All assuming I'm right about the behavior, which maybe I'm not -- I've only barely played with a Falcon, and it was many years ago. John Wilson D Bit