On Mon, Apr 28, 2014 at 5:58 PM, Guy Sotomayor <ggs at shiresoft.com> wrote:
The modular supplies that I'm looking at can put
up to 6 supplies in one
chassis. Each individual supply is independent and has their own voltage
sense.
That sounds reasonable.
So in one chassis there will be 5 -5.2v suppliles.
Each will be
independent with their own voltage sense. I'll duplicate that chassis
configuration
to get to the requisite 10 -5.2v supplies.
I think most KL10 configurations only actually have nine of the -5.2V
supplies, though there's room for a tenth regulator. I'm not sure
specifically about the 2065.
The spec on the ripple is 20MHz and 100mV (or 1.0%
pk-pk).
The 100mV would be no problem for TTL, NMOS, or CMOS, and it would probably
be fine for a single-Vee-supply ECL system, but it is very high for a
multi-supply system. 10K MECL has worst-case noise margin for logic 1 of
only 82mV (Motorola MECL System Design Handbook Fourth Edition, HB205/D,
May 1988, chapter 5: Power Distribution). That worst-case analysis is
based on an output of a part at Vee(max) and an input of a part at
Vee(min). That's exactly the condition you will have for signals crossing
from one power supply domain into another, if the noise
happens to be out
of phase. IIRC there's not too much decoupling capacitance on
the boards,
since they didn't need it. I'm not sure how much of that 1% pk-pk noise to
actually expect at the Vee pins of the chips.
I don't have enough information to say whether you're likely to have a
problem with it or not, but I'd be concerned about it.