On Jan 31, 2021, at 8:19 PM, Josh Dersch
<derschjo at gmail.com> wrote:
Well, what's interesting here is that on my system, switch S4 (MAINT
steps the processor with switches S1 and S2 set to *any*
Hmm, would expect to see S2:1 S1:0 step by microinstruction, and S2:1 S1:1
step by clock phase. The other two settings should free run the
microcode. So yeah, sounds like something fishy there... The TIG card has
more than a few analog components, and its not too unusual for these to get
hung up on the adjacent card and have a leg pulled or sheared from the
Ah, and page II-6-20 (p. 178) indicates that when
DCLO is asserted, it
asserts: "UBCE ROM INIT H - forces the ROM to ZAP.00
(200), and stops and
clears the Timing Generator and the Cache timing."
Yup, that's one of the signals coming in to RAC E106. Probing there
should indicate which of possible sources for ZAP is actually occurring
(UBCE ROM INIT H on pins 2 and 3 there).
DCLO is a classic... Make sure to 'scope it, because it sometimes has
troublesome spikes that don't show on a multimeter. If you have H742s,
there are some wet tantalums on the control board that sometimes leak and
cause trouble with this.
I'm sure you are raring to go -- hope those fans show up for you tomorrow,
and will be interested to hear what you find!
Small update; fans arrived today and they are now installed. Voltages
tested on the backplane at the points called out in the service docs, and
all voltages dialed in to 5.05V. Ripple is within tolerances -- about
200mV with some very short spikes that barely show up on my 'scope that go
to 300mV or so. Not sure if this is abnormal, I also saw these while
burning the supplies in on the bench.
Checked the AC LO and DC LO signals at all the points called out in figure
6-12 (p. II-6-22 of
and appear to be correct. Looked at most of them under the scope and no
spikes (other than those in the ripple from the power supply.)
Tomorrow I'll get some boards out on extenders and take a look at what's
going on at the logic level.