26 Apr
2013
26 Apr
'13
6:28 p.m.
On Apr 26, 2013, at 8:45 PM, ben wrote:
Actually, both FPGA companies provide a lot of the simpler or
more necessary cores (UARTs, SPI/I2C controllers, SDRAM
controllers) for free. It sells more FPGAs and software that
way. I could be a little off-base about those being free with
the "Web Edition" software (the free download version), but last
I recall, they were.
As easy as SRAM usually is. The thing you have to consider
with SRAM on an FPGA is that the latencies in and out of the
FPGA can throw your timing off (you have to worry about the
same things with gates in a 74xx-based PCB design, but you're
already worrying about it for everything else). More or less,
though, it's just SRAM, so if you throw an address at it, you
get data back eventually. It's just the "eventually" part
that can get you.
The SRAM isn't big, but neither is the address space of a
PDP-11 compared to modern machines. It's even 16 bits wide,
which is pretty handy for a PDP-11.
- Dave
On 4/26/2013 5:54 PM, David Riley wrote:
Altera provides a free one that's pretty easy to drop in using Qsys,
if memory serves. You'd have to expend a little more effort to glue
it to something else, especially if you wanted it to behave like an
SRAM (which is something very difficult to do with SDRAM because of
the refresh cycle, which you have to wait for but not all the time).
For things like SDRAM controllers, DDR or not, you'll usually use one
of their IP cores. You should; they're free, and a controller like
that takes a LONG time to implement and debug (if you thought a DRAM
controller in 7400 parts was complex, just wait until you see the
timing calibration stuff that goes into DDR2 and DDR3).
What ip core to use, is my problem. I guess I could order the DE1 board to replace the
DE0.
What was used in the PDP 11 setup I wonder.
You *could*, but I'm not sure why you would. The DE0 is actually
superior to the DE1 in most respects; the DE1 is the old Cyclone II
eval board that the DE0 replaced. Sytse has builds for a bunch of
boards up, including the DE0, DE0-Nano and DE1. The picture from
VCF East last year on Syste's site actually shows it running on a
DE0 in front of Dave McGuire's PDP-11/70 (if I recall, it was
Sridhar running the FPGA demo, but my memory is a bit fuzzy; that
was a busy day!).
The DE1 does have SRAM, though, which the DE0 doesn't. So there's
that.
You might
actually want to look into Qsys, which is Altera's GUI-
driven system generation interface. That actually lets you get up
and going rather quickly with all the interfaces you mentioned
above. When you write your own logic (e.g. a CPU core), it's not
*too* hard to bolt it on using Qsys, which does all the drudgery
of making the buses and address decoders for you.
I am not sure what I can use nowdays, everthing is $$$ for the IP
stuff. It's also
not portable. But it's not a terrible start if you
want to just get up and running with an FPGA and a UART.
I'll be glad to send you a simple UART I made in Verilog that I
reuse in a lot of my projects. It's not fancy, and it doesn't
conform to any standard bus, but it's easy to glue to things. I
can also send you some simple projects for the DE1 board, which
should make for a nice exercise to port to the DE0 board (which
is quite similar in a lot of ways). I also have a peek/poke
unit entirely in Verilog using that same UART to do simple reads
and writes over Wishbone, which is the bus used by a lot of
OpenCores projects (and is nearly identical to Altera's Avalon
bus).
Is the static ram on the DE1 board easy to use?