2 Sep
2014
2 Sep
'14
12:08 p.m.
Just noticed some errors in the CCS DRAM board schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
I've not seen the schamtics, but are they drawn, perhaps, as OR gates
_with inverting circles on the inputs_? Rememebr that a positive logic
AND gate is a negative logic OR gate (De Morgan's lwa, essentially). That
is, if you have 2 active low signals (signals that are true when low/0),
and feed them into am AND gate like a 7408, then output, if considerd
also to be actiuve low, is true is either of the inputs is true
(translation : the output of an AND gate is 0 if either of the inputs is
0). So calling it an OR gate makes sense.
-tony