28 Nov
2011
28 Nov
'11
11:19 a.m.
In article <CAHG8iGU8kEN-WCv7D=vzNUGUDfNZVhaLTD_Hkquv=3d=5gYwEA at mail.gmail.com>,
Jason McBrien <jbmcb1 at gmail.com> writes:
I remember reading somewhere in a memory compatibility
guide that the
refresh rate of the memory modules must be within a certain threshold of
the nominal refresh rate, otherwise the cells loose their charge and you
end up with memory corruption. I believe people were trying to use 133MHz
SDRAM DIMMs in a machine that clocked it's memory at 66MHz, and it wouldn't
work.
Sure, there's an impedance mismatch between the cycle times of the
host system and the required refresh rate of the modern (faster)
memory.
I'm not well versed in memory design, but you
might get it to work with
some buffer circuitry that kept the memory refreshed properly, even if it's
doing nothing for 7 out of 8 cycles.
Yes, sorry I wasn't explicit about what sort of design I was
imagining. I was definitely feeling that there would need to be some
sort of controller on the memory board that mediates between the host
and the modern memory parts -- something to match the timings between
the two worlds.
I wasn't thinking that just hooking the modern chips up straight to
the vintage busses was going to do the trick.
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