14 Nov
2011
14 Nov
'11
8:02 p.m.
On Nov 14, 2011, at 10:37 AM, Keith Monahan wrote:
Yeah. There's a lot to deal with for doing DDR (more so the farther you go, though
it's also easier to make a solution that works first go now, too). We've always
had first-spin success, but we also have (or use, depending on the project) very good
layout people. Sometimes the hardware makes it harder; the Virtex-6 has absolutely awful
DDR3 waveforms, even on their reference platforms. It won't even pass the compliance
tests on Agilent scopes, not by a long shot.
Hm, I'll see if I can find it. I'm not sure I ever used it outside of SOPC
Builder.
Well, DDR is a
pain in the ass. It has a lot of timing constraints
(including a minimum clock speed on non-LPDDR parts because there's a
DLL for aligning the data that has a minimum speed) that are very
hard to match.
And there are board/trace routing issues that you must also take into account. Regular SDRAM
(which is what's on the DE1, at least)
doesn't have any requirements like that as long as you refresh often
enough. Even the "commands" to the controller on the chip follow the
same pattern as their non-synchronous counterparts. I believe Terasic
even includes some free-as-in-beer core to make it behave much like
SRAM on their site and in the materials that come with the DE1.
Can you please point me to this? I have a DE0 as mentioned, and I actually use a
modified FOSS core designed for the DE2, which works fine on the DE0. I'd rather use
an official or better-vetted solution.
I downloaded the DE1 CDROM from Terasic and I don't see it. Their "using sdram
with verilog" sounds really promising, until you figure out that they actually create
a NIOS II core with the memory controller, and then have you access the memory from
verilog through that core.
I even emailed support about this, and they said, "sorry, yes, only through
NIOS." What is frustrating about Terasic Support is that when
I found a problem with VGA support where a certain pin does "double duty" as
both a VGA-pin and a programming pin, the default Altera software fatals out with default
configuration. You need to change something to use the VGA connector. SO I email them,
point out the issue, point out the resolution, and told him to add it as an FAQ. I
probably took me an hour or so to find a working resolution on my own. They've failed
to ever add it to their FAQ......
Right, thought that's a long-standing default with Quartus project files along with
unused outputs defaulting to "output GND", which is a horrifying default from a
"bringing up parts of a board" section; you're almost guaranteed to drive
GND into someone else's logic high. Perhaps they don't change it because
they're afraid of violating assumptions, though I think they might have at least
changed the latter one in recent versions.
Perhaps Terasic assumes you are familiar with the tools (which is a pretty dumb assumption
considering the target market).
- Dave