on FPGA simulation

Oh! That's a very important thing I hadn't known before. I'd been assuming an FPGA was, well, a big chipful of gates which you wired up however you wanted, and which then behaved like, well, the bunch of gates you've wired them up as; whether any of the signals those gates processed could be considered a clock would be irrelevant. I'm glad to have this mental model corrected _before_ I did anything based on it. That's a pretty crippling limitation for many purposes. Quite. I have a boardful of TTL which I designed and built to allow a parallel port to control (via relays, driven off discrete transistors controlled by logic levels) a bunch of mains outlets. There are a few signals which could sort of be seen as clocks - for example, one of them drives the clock input to a shift register - but no global clock that applies to the whole circuit. Would this be unrepresentable in an FPGA - or, rather, would it have to be redesigned to operate with a global clock to be representable in an FPGA? You make it sound like it. /~\ The ASCII Mouse \ / Ribbon Campaign X Against HTML mouse at rodents-montreal.org / \ Email! 7D C8 61 52 5D E7 2D 39 4E F1 31 3E E8 B3 27 4B