16 Nov
2011
16 Nov
'11
6:19 a.m.
From: eric at brouhaha.com
Mouse wrote:
Verilog doesn't deal well with simulaneous clocks into a set/reset latch
that in real life work fine.
It doesn't deal well with anything that is bidirectional, be it resistor,
transmission gate or what have you.
For each of these problems special simulations need to be created
to handle the behavior of that circuit. Differential logic is hopeless.
Self timed logic is a joke.
Still, for just normal logic it can be made to work and that is what
FPGA are intended to do.
Dwight
For example, if a critical piece of the design is
analog electronics,
not digital at all. As a really simple example, it involve a D/A or
A/D converter.
VHDL lets you design such things, as does System Verilog. The FPGA
synthesis tools will certainly tell you that it can't fit it into an FPGA.
That said, it is possible to implement some types of A/D and D/A
converters in an FPGA with only a few external components. There are
application notes about that. Obviously the capabilities are very
limited compared to normal ADC and DAC parts, but there are times when
it is nevertheless quite useful.