DEC KS-10 FPGA

Rob Doyle wrote: The KL10 came in two versions, referred to as "Model A" and "Model B".[*] The difference is that the Model A supports the traditional 256KW user address space, as was found on the earlier KI10 and KS10. The Model B adds the concept of "sections", which adds another 12 bits to the logical address, although the KL10 Model B only implements 5 of them, for a maximum of 32 sections. This expands the user address space to 8 Mwords. Multiple section support involves changes to the way paging works, introducing an additional level of tables. It also adds complications to indirect words, byte pointers, and the PXCT instruction, among other things. The KS10 does not support multiple sections. Its data paths were not designed for it, so there is no efficient way to add multiple section support merely by adding microcode. From a non-system programmer's perspective, the KS10 is similar to a KL10 Model A. The later versions of TOPS-20 simply got too big to fit well on a single-section machine. Eric [*] Note that the "Model A" and "Model B" terminology does not directly correlate with a letter suffix on a KL10 ordering code, like KL10-A. In fact, the KL10-A, KL10-B, KL10-BC, and KL10-C were all equipped with the "Model A" APR ("Arithmetic PRocessor, which anyone else calls CPU), while the KL10-D, KL10-E, and KL10-R were equipped with the "Model B" APR. It gets even more complicated when field upgrades are considered. In hardware terms, the "Model A" has a KL10-PA APR. The "Model B" as a KL10-PV or (later) KL10-PW APR. In addition to the multisection support, the KL10-PV also runs at a higher clock frequency than the KL10-PA. The KL10-PW (standard in 1095 and 2065 systems, or available as an upgrade from the KL10-PV) has a larger cache and larger pager TLB, so it increases the performance slightly more, but doesn't change the programmer's model significantly.