FPGAs and PDP-11's

These problems have arisen from the unfortunate fact that they're easy to fix, though it's not very efficient use of the silicon. Since there's plenty of it, not many of us are concerned about that any more. Since there's a pipeline register in every CLB, you might as well build your circuits as synchronous ones. See my comments below, please. Dick -----Original Message----- From: Tony Duell <ard(a)p850ug1.demon.co.uk> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Monday, August 30, 1999 7:28 PM Subject: Re: FPGAs and PDP-11's i.e. Choosing the pins at the outset isn't as important to me as choosing to have them remain what they become after the first route. points. I'd make two points about these comments. They're right, of course, seen in the proper light, but they're really not the case at all. Taking the second one first, synchronous circuits do not produce glitches. By definition, the outputs are clocked at the same rate as the inputs, which are, if properly designed, clocked so as to let the signals settle between clocks, there can be no glitches. Outputs are clocked, not gated. It's possible to build circuits which have glitches, but not recommended. With a synchronous circuit, the only concern, and it is significant, is the clock skew. Careful planning and cautious design can minimize/mitigate this risk. Additionally, though my experience with this phenomenon is limited, it was considered advisable to let the software determine the pinouts on the first pass through the routing process, thereby making the timing constraints the primary priority for the router to manage. Subsequent routes, particularly changes to other parts of the circuits than the critical pinouts, can be allowed to be automatically assigned as well later, but the important pins held constant, or locked. Since these routing algorithms do strange things, it's still possible you won't get the pin assignment you prefer, your odds are improved in this way. about, Glitches can only occur when transient signals are propagated through a combinatorial stage. If circuits are pipelined correctly (meaning for the circuit in particular, not according to some cookbook) decoders' inputs will be registered, and their outputs will also be registered, hence, they can't generate glitches. Routing delays must be considered, and the skew of the clock can, therefore engender routing races, but these must be taken into account when computing the system clock rate. The clock must be chosen such that it doesn't allow such glitching. Metastability can also become a risk when different segments of a circuit are clocked with different generations of the same clock or with entirely different ones. Mitigation for those hazards must also be provided.