3 Jan
2006
3 Jan
'06
2:09 p.m.
e.stiebler wrote:
Sorry to disagree here. The LUTs are 4 bit wide, so working with 1..4
bits causes the same delay.
No -- they are look up tables. 4 inputs ... 1 output.
What FPGA's don't handle well is wide multiplexers, something CPLD's are
better at.
Ben alias woodelf