1 Aug
2000
1 Aug
'00
7:15 a.m.
William Donzelli wrote:
It seems that VHDL (and Verilog) has moved 99.9
percent away from its
original purpose, that of pure documentation
According to the references I have handy, VHDL was originally intended
primarily for simulation. I can't find a single reference to any intention
that it serve solely as documentation.
As somewhat of a secondary objective, VHDL was intended to support
synthesis; there's a very recent IEEE standard for that.
Verilog was intended for both synthesis and simulation.