On 2013-12-22 10:08, Al Kossow wrote:
On 12/22/13 8:43 AM, Al Kossow wrote:
Here is a first draft. Anything wrong/missing
architecturally?
The one thing that I didn't think of was not handling 18 bit data transfers
on Unibus DMA, though now that I've thought of it adding the data parity
bits
to the buffering wouldn't be a big deal even if there wouldn't be any code
behind it.
Just use SSRAM (cy7c1460, ...) they are easier to deal with,
and have 9/18/36 bit width ...
And as you are connecting them via the FPGA to the ARM,
you should be fine ...