bits and butts

Tom Jennings wrote: ... Post 1964? Why, yes, although I can only just now talk about it since it is past the 10 year cctalk rule. I was an early employee of Chromatic Research, a failed 1993-1999 start up that I believe coined the term "media processor." The MPACT1 and MPACT2 chips contained a LIW processor that had 9b bytes, and all math was 2's complement. The datapath was 72b wide, and most operations could work on eight 9b bytes, four 18b words, or two "36b words" (although the multipliers copped out an only did a 27bx27b multiply). Why the 9-bittedness? There were two reasons. First, Chromatic wrongly foresaw MPEG as being the big draw, and computing ((color component 1) - (color component 2)) required a 9b delta; 16b could have been used, but only four pixels could have been processed per clock. We doubled the peak throughput by adding only 12.5% more datapath resources. The second reason was that the chip used RAMBUS memories, which were only sold with 9b channels, and we had no particular need for parity. Other MPACT oddities: Each 72b instruction bundle had a two bit field that indicated that the pair of instructions had to be either executed sequentially, executed in parallel, executed in parallel "VECLEN1" or "VECLEN2" times in a row (where VECLEN1 and VECLEN2 were registers containing a repeat count). The chip had 512 72b registers, and the programming game was to work on vectors of data in this register while streaming data to/from the RDRAM memory (Chromatic was one of early adopters of RAMBUS memory). The multipliers had various rounding modes, including "round random", where 6b pseudorandom bias was added just below the trucation point, as some audio filter algorithms have better spectral properties with this type of rounding. There weren't separate shift left/shift right instructions, just a shift. Positive shift counts shifted left, negative shifted right. This was especially important since for SIMD data, sometimes different fields had to shift opposite directions in the same instruction. The chip implemented CGA/EGA/VGA in all of their textmode, planar mode, packed mode glory via emulation. All VGA register accesses actually got funnelled into a VGA command FIFO. When the FIFO went non-empty, an interrupt was taken to the VGA emulation routine; it would parse the VGA commands and carry out the necessary work on the flat, packed pixel framebuffer so that the results looked as they should. It seems laughable now when multiple VGA cores would fit on a pinhead, but back then in 0.65 um, a VGA core would have been a significant cost. I guess I'll stop there, although there were a number of other interesting features.