28 Nov
2017
28 Nov
'17
10:27 a.m.
On 2017-11-28 08:54, Noel Chiappa via cctalk wrote:
and the whole thing is here:
https://github.com/dabridgham/QSIC
including the Verilog for the uengine. Dave reports that it should be easy to
adapt his uengine design to other uses, it should run in pretty much any
FPGA. So if you want to build a PDP-15 (or a Multics! :-) in an FPGA, there
you go. Dave indicates he'd be happy to help anyone who needs to tweak the
uengine design for their particular application.
Hopefully someone will find this useful!
Dave has a KV10 already in verilog, so why not port it to the uengine?
;-)