FPGA history (was Re: VHDL PDP11)

I can confirm that the term "FPGA" was used early on and that Xilinx's "LCA" never caught on. Back in 1986 I had a nice chat with someone at the company (I think it was the president, but am not sure) who was very excited that there were people way down in Brazil trying to use their product. It was a lot of fun to use XACT on a CGA 8086 PC to set each logic block individually and route each wire through all the intermediate switches. I couldn't get the design to be fast enough, unfortunately, and had to use TTLs and PALs instead. The XC6200 was a favorite among the academic people (I was just offered two boards with this chip last week) but was never used in any product and was dropped. It had come from outside Xilinx and had never really meshed well with the rest of that company's products: http://www.algotronix.com/people/tom/album.html The reconfigurability came back in a more limited form in the Virtex architecture (and so in Spartan II and later as well) and though the detailed information about the bit files were never released, there was a library called JBits which was made available to selected groups which did give you full control over the configuration bits. This was not updated to handle newer chip families as these became available and eventually JBits vanished. Atmel had two families of FPGAs, the AT40K and the AT6000. They are both tiny and limited by today's standards, but teh AT6000 (if I remember correctly) did have its configuration bits fully documented and for a while I considered using it in my projects for this reason. The VPR academic FPGA tools could be used with JBits to do the whole job on old Virtex chips. http://www.eecg.toronto.edu/vpr/ There was a project to figure out the configuration bits for Virtex chips which was part of a larger project to build a PDP-10 with FPGAs. I don't think either was finished: http://neil.franklin.ch/Projects/VirtexTools/ Here is a series of papers about more recent efforts to generate configuration bits without using the vendor tools: Roman Lysecky, Frank Vahid, and Sheldon X.-D. Tan. 2004. Dynamic FPGA routing for just-in-time FPGA compilation. In Proceedings of the 41st annual Design Automation Conference (DAC '04). ACM, New York, NY, USA, 954-959. http://dl.acm.org/citation.cfm?id=996819&preflayout=flat Etienne Bergeron, Marc Feeley, and Jean Pierre David. Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs. In International IEEE Northeast Workshop on Circuits and Systems (NEWCAS'07), pages 642-645, August 2007 http://www.iro.umontreal.ca/~feeley/papers/BergeronFeeleyDavidNEWCAS07.p df Etienne Bergeron, Marc Feeley, and Jean-Pierre David. Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. In International Conference on Compiler Construction (CC'08), volume 4959 of Lecture Notes in Computer Science, pages 178-192, March 2008 http://www.iro.umontreal.ca/~feeley/papers/BergeronFeeleyDavidCC08.pdf Etienne Bergeron, Louis-David Perron, Marc Feeley, and Jean Pierre David. Logarithmic-Time FPGA bitstream analysis: A step towards JIT hardware compilation. ACM Transactions on Reconfigurable Technology and Systems, Vol 4, No 2, Article 12 (May 2011), 27 pages http://dl.acm.org/citation.cfm?id=1968502.1968503&preflayout=flat -- Jecel