29 Mar
2019
29 Mar
'19
1:47 p.m.
From an emulation standpoint, latch or flop is not
necessarily an issue. It is that it is a state holding element. The only potential issue
is if he was doing clock cycle emulation. He'd need to understand what was originally
considered a clock cycle.
Dwight
________________________________
From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Paul Koning via cctalk
<cctalk at classiccmp.org>
Sent: Friday, March 29, 2019 9:51 AM
To: Jon Elson; General Discussion: On-Topic and Off-Topic Posts
Cc: Ken Shirriff
Subject: Re: IBM 360 Model 50 information?
On Mar 29, 2019, at 11:18 AM, Jon Elson via cctalk
<cctalk at classiccmp.org> wrote:
...
Oh, one other issue is the 360's had no FFs. All storage elements were transparent
latches, and they generally used a 4-phase clock.
The same is true for the CDC 6600. Not a big surprise; a transparent latch can be made of
two cross-connected gates, while a flip-flop (edge triggered) requires more stuff (four
gates?). And the 6600 uses at least four clock phases; in parts of the CPU there are
additional clocks so some of the hairy parts are more like 6 or so phases.
paul