17 Nov
2011
17 Nov
'11
1:15 p.m.
David Riley wrote:
Plus, when you have multiple paths going through your
device with different propagation delays (FPGA or PCB),
different flip-flops can catch different values on the same
clock edge because they catch the data at different points
in time (often one after it has flipped, and one before it).
This can sometimes be observed with off-the-shelf chips. For instance,
suppose you have a 6502 system with an input port that simply gates
unsynchronized input data to the bus using a tristate buffer. If you do
an LDA from that port, and the port data changes violating the input
setup time, you can get a situation where the loaded accumulator value
has the MSB set, but the N flag is not set, or vice versa.
Eric