27 Apr
2013
27 Apr
'13
11:02 a.m.
On 27/04/2013 17:12, David Riley wrote:
On Apr 27, 2013, at 10:48 AM, ben wrote:
Dave
I assume the tool chain is like the Xilynx one. So you can see the
generated routing on the chip and even edit it if desired. These are
absolutely amazing tools. I am sure its going to take me a long time to
get really up-to-speed on them, but already I can see a huge potential
for doing those sort of jobs where you just need several things to
happen at once, or where a Pic or Arduino just isn't fas enough...
Dave
G4UGM
I don't do the other brand. -:)
I do
both. They're fine. Xilinx used to be lagging way behind
on device features (but way ahead in market share), but they've
really caught up with Altera with the 7-series. The I/O bank
structure is SO much easier to plan around now. I find myself
recommending Xilinx devices for the first time in five years
now.
I am finding out that you get what you pay for
... modern junk with no docs.
Sorry? There are PLENTY of docs.
I want to know basic things, I don't like the
modern bloat needed
just to work. What happens on Power up? What happens if I want 5 volt I/O? What clock
speed is the FPGA ? Is the PLL driving SDRAM pins or something else?
All of these
are described in the device handbook. It's here:
http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf
What is the priority of logic expressions in
hardware description language?
In Verilog or VHDL, it's pretty explicit and
very C-like.
If you want to see how the synthesizer turns various language
constructs into hardware, see the synthesis manual:
http://www.altera.com/literature/hb/qts/qts_qii51008.pdf
- Dave