16 Nov
2011
16 Nov
'11
11 a.m.
On Nov 16, 2011, at 1:38 PM, Mouse wrote:
It's not entirely true, but FPGAs are definitely designed to run synchronously. You
can run as combinationally as you want, but it's not optimized for that and you'll
drive the tools nuts.
An FPGA is basically a bunch of LUTs which can optionally feed out to either a clocked
register or directly to the routing lines. Take a look at the architecture manual of
something sometime (Altera's Cyclone manuals are probably a good place to start) and
it'll give you a good overview.
It should be doable, but you might be able to achieve better performance, etc. if you were
to make it as synchronous as possible. You can certainly have signals that run straight
into a pin, go through a whole lot of combinational logic, and come out another pin with
no clocks whatsoever.
- Dave
[...] almost
all FPGA implementations must have a clock of some sort.
Oh! That's a very important thing I hadn't known before. I'd been
assuming an FPGA was, well, a big chipful of gates which you wired up
however you wanted, and which then behaved like, well, the bunch of
gates you've wired them up as; whether any of the signals those gates
processed could be considered a clock would be irrelevant. Not every
design employing logic is a CPU and not all employ clocked
logic.
Quite.
I have a boardful of TTL which I designed and built to allow a parallel
port to control (via relays, driven off discrete transistors controlled
by logic levels) a bunch of mains outlets. There are a few signals
which could sort of be seen as clocks - for example, one of them drives
the clock input to a shift register - but no global clock that applies
to the whole circuit. Would this be unrepresentable in an FPGA - or,
rather, would it have to be redesigned to operate with a global clock
to be representable in an FPGA? You make it sound like it.