16 Nov
2011
16 Nov
'11
2:43 p.m.
On 16 Nov 2011 at 16:47, David Riley wrote:
My biggest pet peeve about FPGA design tools is the
warnings they put
out. You generally can't tell it "hey, this module is parameterized
and generic so in this instance I'm not using this output", so
anything you make properly generically will end up burying the real,
important warnings in a sea of noise. You can't even use vendor IP
(I'm especially thinking of memory controllers) without generating
over 100 warnings, which drives me NUTS. I don't like combing through
my synthesis report to see which of 800 messages is important.
...or even the same number/type of warnings between various vendors'
tools. I tend to take warning messages very seriously, particularly
during the implementation phase. Maybe I'm just being paranoid.
-------------OT-----------------------------
Just heard the news bulletin from the Beeb world service in the
background--IBM apparently has a ("Kights Corner") coprocessor chip
that runs at a teraflop:
http://www.bbc.co.uk/news/technology-15758057
Cheers,
Chuck