1 Sep
2014
1 Sep
'14
7:18 p.m.
On 2014-Sep-01, at 5:28 PM, drlegendre . wrote:
bar-over-<symbol> means "the complement of", generally read as
not-<symbol>.
e.g.:
bar over Q is not-Q.
No, not active high, it actually often means active low.
e.g.:
PWR is processor-write (write sig from processor)
bar over PWR == not-PWR
== not processor write
== active low processor write
== processor write is active when this line is low
My own personal standard for purposes of textual representation is to prefix the name of
an inverted signal with lowercase-n.
e.g. not-PWR --> nPWR
There are other standards, all of them with their own benefits and detriments.
Going backwards:
- U9 is the refresh address counter.
- The bus RFSH signal is gated through U7-pins8,9,10 to increment U9, but it is also
incremented through U16 (div-by-10), U6-pin9.
- U16 is clocked by bus phase-1 or phase-2. U16 appears to implement the
delay-between-refresh cycles.
It doesn't need an on-board oscillator because it's using the bus clock sigs
(phases).
2MHz from the bus divided by 10 via U16 = refresh cycles at a 200KHz rate.
200KHz divided by 128 or 256 in U9 gives a regeneration period in the ballpark of a
millisecond for each row, which is about right for the chips.
Usually when a board uses the RFSH signal, it uses the refresh address a Z80 is putting
out on the address bus rather than it's own counter.
I haven't examined it enough detail to be sure the onboard refresh is *entirely*
self-supporting, but it looks like it is.
You could try scoping U14-pins1,19. If the refresh circuitry is active there should be a
repetitious pulse there on the order of 200KHz, gating the refresh address onto the DRAM
chip address lines.
Thanks for the input again..
On Mon, Sep 1, 2014 at 6:21 PM, Brent Hilpert <hilpert at cs.ubc.ca> wrote:
To start in on
board-level debugging, one thing to check: if the board is
enabled and a valid address for the board is on the bus, then U4 pin 8
should be high.
Hey cool, that's the kind of info I need to keep me going. I'll take a
look
at that in a bit.. or, take a look at that bit in a while or something.
So here's a question or two. First off, how do you pronounce a letter
designation with a line over it - like the outputs of a flip-flop are Q and
(Q with overline). Do you say "Q high" or "Q prime".. "Q
complement" or
what? What about when a named signal such as CLOC or PWR has an overline?
Do you pronounce it "CLOC active high" or something?
(Does that line actually mean "active high"? - that's what I've
surmised..) Finally, on the CPU board, pin 49 supplies the CLOC
signal.. but it's
actually pins 25 & 24 that the DRAM card look to for +its+ clock signal.
Those pins are marked with what looks like a ?-1 and ?-2 (Greek Phi),
respectively. Is that actually a 'phi', and if so, what does it mean - what
are those signals, if not clock signals? And how do you pronounce them? It
could be a slashed-zero, too... "?".
(Generally Theta (?) is used to denote a phase /
angular relationship or
quantity. it looks kinda like phi, but it's not.)
Yes, it is phi, and is pronounced as phase-1, phase-2, etc.
Yes, it is derived from the physics/math angular relationship, as it generally refers to
repetitious (clock) signals with a phase (angular) displacement from each other.
For the bus, not-CLOC (pin 49) is the raw clock, two clock phases are derived from this,
put on pins 24 & 25.
I haven't
examined the schematic in enough detail to quite convince myself
for sure the board will work without the RFSH signal, but that would affect
the writing/retention.
I'm a bit confused.. all DRAMs need a refresh, and the doc for this board
is pretty explicit that it needs "the correct" (ugh!) phase of the clock
signal "on pins 24 & 25". Why would you think the board doesn't
require
such a signal, that it has its own on-board refresh hardware? FWIW, there's
no crystal on-board to control an osc. to that level of precision.