16 Nov
2011
16 Nov
'11
7:28 p.m.
On 16 Nov 2011 at 18:44, Eric Smith wrote:
> I've done a limited amount of asynchronous
logic in Spartan-3
FPGAs.
Xilinx says don't do it, and the static timing
analysis tool throws up
its hands, but with a little effort it seems possible to do it.
However, I wouldn't want the job of implementing a large async circuit
in an FPGA. Life's too short.
Do you think you'd have any trouble working up an implementation of
this 19-year old design in FPGA?
http://brendaluderman.info/cv/papers/An_Asynchronous_Multiplier.pdf
Nothing big, say 32x32 bit.
I'm just trying to figure out how far this FPGA thing can be pushed.
--Chuck