7 Dec
2015
7 Dec
'15
1:26 p.m.
And regarding timing... even this drive works without any problem:
=== P8000 WDC Emulator 0.93 ===
INFO: PATA init start
INFO: PATA disk has been found
INFO: Number of logical cylinders: 1001
INFO: Number of logical heads: 15
INFO: Number of logical sectors per logical track: 34
INFO: Serial number: 00DG169020
INFO: Firmware revision: 05.05.01
INFO: Model number: ST3290A
INFO: Capabilities:
Its releasedate should be somewhere in 1994. So it predates the drive
I have problems with for two years:
=== P8000 WDC Emulator 0.93 ===
INFO: PATA init start
INFO: PATA disk has been found
INFO: Number of logical cylinders: 3148
INFO: Number of logical heads: 16
INFO: Number of logical sectors per logical track: 63
INFO: Serial number: WD-WT2891920914
INFO: Firmware revision: 23.16U73
INFO: Model number: WDC AC31600H
INFO: Capabilities: DMA, LBA, IORDY may be disabled, IORDY, Standard
standby Timer values,
INFO: User addressable sectors for 28-bit commands: 3173184
Single Word DMA modes: 0
Multiword Word DMA modes: 1031
PIO modes: 3
INFO: Minimum Multiword DMA cycle time per word: 120ns
INFO: Recommended Multiword DMA cycle time: 120ns
INFO: Minimum PIO transfer cycle time without flow control: 160ns
INFO: Minimum PIO cycle time with IORDY flow control: 120ns
INFO: Additional support: 0
ERROR: read error at address: 0 / errorcode is: 04
Other WD drives I own from '98 and '99 also work. Also a Samsung 560MB
drive from 1995 which is also doing LBA works fine.
Regards, Oliver
Oliver Lehmann <lehmann at ans-netz.de> wrote:
Hi,
OK, i tried now to set Drive/Head first before I set all the other
registers. No success.
I then added a 10ms delay after the data is set for each register,
disable /WR and then wait another 10ms before I execute the next
register.
I also added status checks after each register setting. It stays 0x50
everytime I check it and just after I issue the command it goes to
0x59.
Feel a bit clueless here :/
Oliver
Oliver Lehmann <lehmann at ans-netz.de> wrote:
> Hi Toby,
>
> Toby Thain <toby at telegraphics.com.au> wrote:
>
>> I think Jon is probably on to something.
>>
>> You can check out the delays in my PIO bit-banging code here:
>> http://www.telegraphics.com.au/svn/picide/trunk/
>>
>> I tested it on a few drives & spent a lot of quality time with the
>> spec...of course I can't guarantee it would work for your specific
>> drive, but it might give you a clue where a delay is missing.
>
> I think that what goes wrong in my code is the pure reading/writing
> stuff since the IDENTIFY command works without any problem. So I
> checked checked your ASM code for the PIC specific for that purpose.
>
> From what I see in "ide_lbacmd" in ide.asm, you wait for BSY and DRQ
> to get low, via "ide_devselect", then issue the drive+head register,
> wait again for BSY and DRQ still in "ide_devselect" . Then, back in
> "ide_lbacmd" you issue the other sector/cyl/head registers. Right
> after that you issue the command to execute without any further
> waiting.
>
> Now is the point where I get the error bit - so how the data is read
> is probably not important here.
>
> I'll tra to "redo" your code tonight, but beside that you issue the
> drive+head first and I do just before I issue the command, I don't
> see a big difference here.
>
> I wonder if I could query the drive for the sector/cyl/head data it
> works with to see if they where recieved correctly. I guess it just
> gets invalid data for at least one of this so it response with ERR
> for any read or write command because of "invalid addressing" (I
> think).
> Do you know if there is a way to find out what sector/cyl/head the
> drive tried to process the command?
>
> Regards,
> Oliver