2 Jul
2012
2 Jul
'12
1:24 p.m.
On 2 Jul 2012 at 18:09, Oliver Lehmann wrote:
Output -> VCC 5.23 MOhm
Output -> GND 5.20 MOhm
VCC -> Output 11.21 MOhm
GND -> Output 11.20 MOhm
Interesting--so they're apparently using a "naked" totem-pole output
stage with no pullup. Interesting--I thought that Zilog always
specified at least a 10K pullup on the clock input.
Rules were made to be broken, I guess.
--Chuck