8 Jun
2010
8 Jun
'10
7:21 a.m.
On 6/7/2010 6:36 PM, Eric Smith wrote:
The flip-flops may be driven by the external clock
input, but often this
is not the case. Almost all modern FPGAs contain either PLL or DLL
blocks that can be used to synthesize other clock frequencies from the
external input.
Right. I've used Xilinx's DCMs before. They are pretty simple and
provide a wide range of output frequencies. My eval board has a single
SMA connector on it for high frequency connections. The forty free I/O
pins use a hirose FX2 connector, not sure what the highest frequency is
available there. I wouldn't think even to 100mhz?
On the FPGA eval boards with a 50 MHz oscillator, I
routinely run the flip-flops of my designs at frequencies up to 200 MHz.
My real point to the original poster was that they don't run at ghz
speeds. Or even close.
Despite looking at the datasheet this morning, I have no idea what the
maximum frequency of my Spartan-3E XC3S500E-4FG320C, speed grade -4 is.
I've fed the coregen DDR controller at 100mhz before, but never used
anything faster.
Thanks for correcting me, I've still got a lot to learn.
Keith