On 6/5/10 3:52 PM, Nigel Williams wrote: Edusystem-50 (TSS/8) was developed to run on that model. It took a lot of effort at the University of Wisconsin to have DEC ship us an 8/e instead, since by that time the 8/i was pretty long in the tooth. It also let us add an RK8-E later on for secondary storage, which is reflected in the UWM monitor code that is on bitsavers. Adding the RK made the system self-hosting. You would take down TSS/8, bring up OS/8 and rebuild the system.

On Jun 5, 2010, at 8:22 PM, jim s wrote: oops. I forgot to include the pli directory. I fixed that and put a new snapshot. The pli code is the "c" code which implements the behavioral models for the IDE disk and the RK05 (as well as ram). -brad Brad Parker Heeltoe Consulting 781-483-3101 http://www.heeltoe.com

Hi, sorry for the interference... but I'd like to comment on this as well :-) A pure CPU? A few days. Not more. But... I haven't written a pdp11, only an 8 in VHDL. It took me a few days (3,4?) to get a pdp8 CPU passing the basic tests. But that was less than the beginning of the hassles: What about front panel? Peripherals? Which options to support? All that tends to be more complicated to decide and build (frontpanel..!) than implementing the raw processor. There's a big gap between a running CPU and a system running an operating system. Puh. Here's a pessimistic estimation: One cycle for every instruction plus one cycle for every memory access. Makes something like 6-7 cycles for a memory-memory indirect addressing instruction with increment or decrement or something alike. On a Spartan-3 you can run it with approx. 100MHz if carefully designed. There are faster FPGAs as well... Anyone here who can calculate actual numbers? For a pdp8/e I've practically proven approx 120 times faster than the original - and still slower than SIMH on my PC... I did it for fun. I always wanted to design a processor - so it became something pdp8 like. I assume that Brad did not have much other reasons. Best wishes and a nice day, Philipp

Yes, but there isn't something you can actually touch. It's just an emulator... BTW I just had a crashed RK05 a few minutes ago - had to clean head and disk... now running fine again... Hey, it's reconfigurable logic! And yes, it's slower than a multi-GHz PC processor with all it's tricks to execute code even faster than you assume. There might be FPGA hardware that can run as fast as 400-500MHz I suppose - but that's still far from a modern PC cpu. On the other hand it's no problem to put a few more pdp8 CPUs into one FPGA... FPGAs can do everything in parallel - and they consume less space and power than the whole simulation environment. :-) Of course! Currently I'm still worrying about that RK05 disk I'm just dumping... Hope it gets through before I have to clean it again... There is still some noise - but no read errors so far... Best wishes, Philipp

Keith wrote: You make it sound like, a PDP 8 with 4K of core has no useful use at all. :) Looking back with the emulators, of vintage hardware it is the fact that expensive things like mass-storage could be shared among several people. I have just been installing some PDP 8 software on a IDE drive and even with the small size of PDP 8 disks ( 2048k max ) you sure can see how small programs and data was back then. With a PDP 8 multi-tasking the programs I expect where dog slow, but they could run with larger memory and disks a larger machine could justify.

On 6/7/2010 6:36 PM, Eric Smith wrote: Right. I've used Xilinx's DCMs before. They are pretty simple and provide a wide range of output frequencies. My eval board has a single SMA connector on it for high frequency connections. The forty free I/O pins use a hirose FX2 connector, not sure what the highest frequency is available there. I wouldn't think even to 100mhz? My real point to the original poster was that they don't run at ghz speeds. Or even close. Despite looking at the datasheet this morning, I have no idea what the maximum frequency of my Spartan-3E XC3S500E-4FG320C, speed grade -4 is. I've fed the coregen DDR controller at 100mhz before, but never used anything faster. Thanks for correcting me, I've still got a lot to learn. Keith

On 6/8/2010 8:13 AM, Philipp Hachtmann wrote: Currently my PDP-8e compatible design on an Altera CycloneII EP2C20 takes about 9% of the total available resources (using internal block ram for the first 4Kx12 memory; pages 1-7 use the external on-board SRAM). So there is lots of logic left to implement peripherals. I have the RX8e/RX01 controller passing the DIRXA diagnostic now, and am in the processing of implementing the backing store on the SD card, so hopefully in the next few weeks I'll get to boot an OS8 image from a floppy image. My PDP8e design runs at a basic 145MHz clock tick (this is a 4Kx12 config only, no external SRAM), and there are four clock ticks per instruction state (thus about 27.5ns for a major state duration). However, to get the memory expanded to the full 32Kx12, I use the 10ns external SRAM, and slow the clock down to 80MHz (12.5ns) per tick. SIMH still runs quite a bit faster, however (by 2X or more). For the PDP8 architecture, SIMH on a fast CPU will probably always be faster than a 'simple' FPGA state machine emulation of the architecture. To make the inherently slower FPGA be able to outspeed a much faster CPU, one would have to go to a much more parallel implementation (ie, a pipelined/superscalar PDP8 design) that is able to make up for the lack of raw FPGA lock speed. Such a PDP8 design is probably going to be very difficult, as the nature of the PDP-8 architecture is not very amenable to either pipelining or superscalar execution. It would certainly be a 'fun' project to consider, but my suspicion is that after implementation one would find so many bubbles/wait states get inserted into the pipe to make the instructions execute correctly there would not be much speed advantage gained. It would certainly be an interesting design study, however. Don PS: BTW for those ever considering implementing an RX floppy interface for the PDP8 and want to run diagnostics, I did find a coding error in the DIRXA (both rev C and D) diagnostics. In one specific test the XDR IOT is being issued before checking for transfer request via the XTR IOT. There is a simple patch to the diagnostic to fix it. Turns out it runs OK on real hardware because the speed difference of a real PDP8e vs a real RX01/2 controller, but if you speed up the RX controller past a certain point the test will always fail.

Torfinn Ingolfsen wrote: Exactly that. I've got one of the Digilent S3 boards as well, but started doing development on the DE1 instead since it has the SDCARD socket on the board, and I can run the whole thing from USB for power. At some point I'll probably port the code to the S3 board (shouldn't be that hard, haven't done anything that is really Altera specific in the code).

At 10:50 AM 6/9/2010, Ben wrote: The assembler, loader, etc. are all part of the standard OS/8 distribution. Documentation? You're probably looking for the OS/8 Software Support Manual. <http://www.dbit.com/pub/pdp8/doc/>http://www.dbit.com/pub/pdp8/doc/ has a bunch of useful OS/8 documents; see ssm.doc, for example. (These '.doc' files are text files.) -Rick

Philipp Hachtmann wrote: I got the doc's I need downloaded. I just have to figure how to print them under windows 2 pages per sheet. The other thing is I have to pick up a bunch of paper tomorrow so I can write out my program. With the 8 you just can't create programs on line.

Ben wrote: I think that will be news to the thousands of programmers that did exactly that.

On 10.06.2010 19:31, Eric Smith wrote: Thousands... and one more! There is a subtle difference between "can't" and "it's sometimes not funny to" :-) -- http://www.hachti.de

Dave McGuire wrote: Well I am one of the people that need to write a program down on paper, rather than compose it on line, using a line editor. That reminds me I, have to set the TTY to do ^H Space ^H later today rather than \?\

There are many things that you can do IFF you are unaware that they can't be done. The Wile E. Coyote principle of software development. Fortunately, I had already created my white on black font BEFORE HP told me that it was impossible.

Stop buying shit parts. -- Will

There are PLENTY of transformer shops out there that will make whatever you want in quantity. Otherwise, there is PLENTY of old stock floating around. -- Will

Mr Ian Primus wrote: GET #$@! CAPS LOCK KEY OFF ... You can tell I writeing CODE. It is the Hammond products that are giving problems. The power transformer seems to unbalanced, one leg with a higher voltage than the other. I got 10H 40ma choke that does not work well, I have a 30H 40 ma choke on order.

Or in my case, I didn;'t realise that many and tried and given up trying to figure out the HP9100 calculator... -tony

Ah an example of the Bumble Bee principle. Aerodynamically the Bumble Bee can't fly. However they have no way of telling the Bee, so it carries on flying. -----Original Message----- From: cctech-bounces at classiccmp.org [mailto:cctech-bounces at classiccmp.org] On Behalf Of Fred Cisin Sent: 10 June 2010 19:32 To: General Discussion: On-Topic and Off-Topic Posts Subject: Re: Programing PDP-8 assembler - details There are many things that you can do IFF you are unaware that they can't be done. The Wile E. Coyote principle of software development. Fortunately, I had already created my white on black font BEFORE HP told me that it was impossible.

On Jun 6, 2010, at 7:02 AM, Jerome H. Fine wrote: um. I already did that. It took a few years, but I only worked on it sporadically. It currently boots (in simulation) RT-11, RSTS V4, BSD 2.9 and V6. I have not debugged the split I & D but it's there. If you send me a RK05 image with TSX on it I'll try and boot it in sim. The last FPGA version I did had no MMU but it did boot RT-11. It had some disk problems which I have since corrected. I believe I could synthesize and run the "no mmu" version pretty quickly. The mmu version need still needs some work do make 50mhz timing. Well, as I said, the no-mmu version runs at 50MHz. I could improve that. The mmu version probably won't run faster, mostly due to the 20ns rams on my fpga board. back in the day I spent a lot of time on TSS/8. I wanted to run it again :-) And, I want to work on cpu's when I grow up. I also spent a lot of time on RSTS and TSX, hence the pdp-11. I know the s/w sims are better, but I like hardware and love running h/w simulations. -brad Brad Parker Heeltoe Consulting 781-483-3101 http://www.heeltoe.com

On Jun 7, 2010, at 7:59 PM, Jerome H. Fine wrote: The current design has an mmu. I has all the guts for a full I&D 11/44 style mmu. I didn't go to the limit and add all of the 11/70 features, but may some day. It's currently configured as a 11/34 style mmu with no split I &D, using defines. Well, the basic clock is 50Mhz, which is 20ns. Each instruction takes a minimum of 3 clocks. The most complex take about 20 clocks. So on average I think it's about 5 clocks/instruction. My last stab said about 10MIPS. So, I think it will beat a 11/44, but won't compare with simh on a modern pc. The disk controller makes an IDE disk look like a single RK05 drive. You can just copy a simh rk05 image onto any ide disk and go. I used basic+, as well as Whitesmith's C under RT-11. Most of the TSX-11 work I did was in Pascal, with a little bit of macro driver work. I also did a lot of fortran on a a standalone 11/23 in a geology lab using RT-11. I wrote a great spacewar clone in fortran which used a scope with z-control :-) brought all the grad student's progress to a complete halt, which didn't make me popular with the dept. head. I'm afraid I can't help with .Chain semantics. -brad Brad Parker Heeltoe Consulting 781-483-3101 http://www.heeltoe.com

On 6/8/2010 4:32 PM, Henk Gooijen wrote: Henk, I think I've seen those XESS boards before. Don't remember where, maybe advertised in circuit cellar or nuts and volts. Their website seems pretty goofy and for the most part doesn't work for me in firefox, so I'm not sure. I've enjoyed learning about digital logic and FPGAs. There is a fair bit to know. I've found verilog pretty straight forward to pickup. Once I get a better handle on it, I'll probably try my hand at VHDL as well. The Spartan 3E board I bought has a bunch of connectors, and built-in support chips. http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD I've been working on a USB external amiga floppy drive controller for the PC. Read and create emulator .ADF images from floppies using a standard PC 3.5" drive. I first used a Parallax microcontroller, and then recently switched to an FPGA solution. Both work now. http://techtravels.org/amiga/amigablog/ Keith