28 Nov
2011
28 Nov
'11
4:12 a.m.
Am 18.11.2011 02:26, schrieb David Riley:
you actually know what the implications are and accept
them, it's
fine (as with so many things that are "no-nos" in engineering).
Couldn't have been said better!
In VHDL I mix signal and variable assignments in processes. I've been
told *NEVER* to do that because it leads to unpredictable results -
wrong, you just have to understand what's going on. Then it's perfectly
save to mix variable and signal assignments.
:-)
Philipp