yet another pdp-8 in a fpga, but this time running tss/8

Hi, sorry for the interference... but I'd like to comment on this as well :-) A pure CPU? A few days. Not more. But... I haven't written a pdp11, only an 8 in VHDL. It took me a few days (3,4?) to get a pdp8 CPU passing the basic tests. But that was less than the beginning of the hassles: What about front panel? Peripherals? Which options to support? All that tends to be more complicated to decide and build (frontpanel..!) than implementing the raw processor. There's a big gap between a running CPU and a system running an operating system. Puh. Here's a pessimistic estimation: One cycle for every instruction plus one cycle for every memory access. Makes something like 6-7 cycles for a memory-memory indirect addressing instruction with increment or decrement or something alike. On a Spartan-3 you can run it with approx. 100MHz if carefully designed. There are faster FPGAs as well... Anyone here who can calculate actual numbers? For a pdp8/e I've practically proven approx 120 times faster than the original - and still slower than SIMH on my PC... I did it for fun. I always wanted to design a processor - so it became something pdp8 like. I assume that Brad did not have much other reasons. Best wishes and a nice day, Philipp