Oregon Status University constructed a general purpose computer (Nebula) in the mid 60s
that used Corning glass delay lines both to construct a 4k x 34 bit main memory with an
auxillary 2k Content Addressable Memory with 32 bits plus some 'tag' bits.
Al archived a copy of the hardware manual on bitsavers
). This manual
doesn't give much detail on the physical hardware implementation, but there is design
(part of the PhD thesis of designer.) If anyone has further interest, I will do a scan of
the 'design' manual which has much more detail and some schematics. I am away on
travel at the moment but can upload in about two weeks.
At the time I was at OSU, Nebula was one of the fastest computers, measured by clock speed
(27 MHz) but slowest by instruction cycle time (100uS) due to being fully bit serial.
Lots of 1000-series mecl parts to do the 3 nS cycles needed for the memory bit times in
the CAM but the rest as a mix of transistor, DTL and TTL devices.