4 Oct
2012
4 Oct
'12
8:54 p.m.
On 10/4/2012 9:49 AM, Rob Jarratt wrote:
Rob,
I have no experience in Verilog or FPGAs, I have little time, but I would
love to learn more about this field as I have some projects of my own I
might wish to do in the future, so would love to get involved if I can
contribute in some way. Just wondering why not the KL though? I think the
later versions of TOPS-20 run this and I would like to run those versions
particularly as I *think* DECnet might only run on the KL.
Regards
I looked at the KL, the KS10, and the Foonly docs before deciding. I
chose the KS10 simply because I think I can implement it in an FPGA.
I used a KA10 so my experience with TOPS-20, DECnet, and paging is nil.
Having said that; there is nothing wrong with adding KL features
to the KS. Half of the microcode address space is unused on a KS
so we can easily double the amount of microcode, if necessary. We
can easily add hardware, too.
For the experts out there:
What exactly are the architectural differences between a KS and KL?
Why does TOPS-20 and DECnet only run on a KL? What would need to be
added to a KS to support DECnet, etc? I guess it never occurred to
me that the applications and OS supported by a KS and KL would be
different...
Rob.