13 Nov
2011
13 Nov
'11
1:23 a.m.
On 11/12/2011 9:41 PM, David Riley wrote:
On Nov 12, 2011, at 9:24 PM, jim s wrote:
Regarding GHDL - the GNU VHDL Compiler:
I do a fair bit of simulation of my PDP-8 using GHDL. It compiles code
10x faster than any other tool I've ever seen - so it's nice for doing
syntax checks.
GHDL is a compiler, as such it compiles VHDL directly into an
executable (in Linux, at least) so it executes very fast. You can do
weird things like link VHDL with C/C++/ADA code. I plan to use that
feature to do an FFT analysis on the data produced by an FPGA doing
some DSP work. Since is just a compiler, GHDL cannot synthesize
anything.
It's perfect for building a PDP-8 simulator. Write the RTL of the
guts in VHDL, wrapper the guts with a simulation environment using
your favorite high-level language. The simulation environment could
have disk drives, virtual TTYs, other devices, debugging hooks, trace
buffers, logic analyzers. When you're happy with how the guts work,
synthesize it. If SIMH had only been written in VHDL...
Its weekness is that too many types of errors (two sources driving a
net, for example) cause it to 'core dump' instead of producing a
meaningful error message. When that happens, it's time to use one of
the other tools to debug.
The author and a couple of gurus are around and answer questions - so
it's supported as well as anything.
GHDL is not the solution to every problem but it is a useful tool in
the toolbox.
Rob.
I wonder if someone can point me to what steps
one needs to use this. I wonder if there is open source / reasonably priced tools to take
the source -> workable code.
I found a gnu vhdl compiler that seems to do some things.
also there is a macro11 assembler required, and i've never had that either.
Open source, no. But both Xilinx and Altera offer the compiler tools (runnable on
Windows and Linux) needed to run on all their low-cost devices (and some of their high-end
ones) for free; for Xilinx, it's called the ISE WebPack, and for Altera it's
called the Quartus II Web Edition. Both are free for use.
In addition, all of the Terasic boards (the Altera ones) mentioned on the guy's site
have the FPGA JTAG programmers built into the board; all you need is the USB cable (which
most of them come with). I can personally vouch for the DE1; I have two of them and I
love them to pieces, even if they are getting a little long in the tooth. The DE0 Nano
will get you a lot more FPGA for half the money, but it's a little harder to interface
to. The DE0 is a nice point in between them as far as price and features, but it has a
little less FPGA than I'd like (that said, you can do an awful lot in 15k LEs).
The GNU VHDL compiler is fine for simulation, but it's not meant for hardware
implementation; typically, that sort of thing has to be done with vendor-specific tools
(some tools, like Icarus Verilog, will produce netlist intermediates (similar to object
files) which the vendor tools can turn into hardware, but it's not common amongst free
tools).
Macro11 is the PDP-11 assembler. Older versions of GCC and GNU binutils (up to either
4.4 or 4.5, IIRC) still had PDP-11 tools you could build, though I don't think the
PDP-11 gas (GNU assembler) is Macro11 compatible.
I haven't yet looked at the source (no time so far), but I would assume it comes with
project files (.qpf for the Altera ones) which the tools can open and build.
I should warn you: coming from a pure software background into FPGA development is a very
sharp transition. It's not software, no matter how much my company's clients
might like to think it is. It doesn't work the same way at all; "software
people" can learn FPGA design, but they will have to un-learn a lot of assumptions
about code before it makes any sense. It's honestly a lot more like writing up the
netlist to a circuit board at a slightly higher level.
- Dave