29 Apr
2014
29 Apr
'14
8:16 p.m.
On Tue, 29 Apr 2014 02:16:13 -0600 Eric Smith wrote:
On Mon, Apr 28, 2014 at 5:58 PM, Guy Sotomayor <ggs
at shiresoft.com> wrote:
Fortunately, it's not quite as bad as that.
MECL 10K signals are referenced to VCC (0V), not VEE (-5.2V). The
single-ended high logic level is driven from an emitter follower that
has nothing to do with VEE, so VEE variation won't affect the logic
high level.
On the receiving gate, the high level is compared against an internally
generated VBB reference. The VBB reference is effectively created by a
resistor divider. The divider is 907 ohms to VCC and 4.98K ohms to VEE,
so the drop across the 907 ohm resistance will change by about 15% of the
change in VEE. A 100mV change in VEE will result in a 15mV change in VBB
and that steals from the noise margin.
The 84mV noise margin in the Design Handbook assumes a 10% variation between
VEE supplies, but the baseline logic high noise margin for 10K is 125mV.
The logic low will have a VEE dependence of about 30% (245 ohm to VCC vs.
779 ohm to VEE).
Both logic levels will have some shift with VTT (-2V) due to the base
current of the emitter follower (I don't know the typical gain of those
transistors) and the Vbe variation with current, but those will be very
modest.
I am not intimately familiar with the KL10 schematics yet. Does it pass
single-ended signals between power domains, or does it use differential
for those?
The power supplies I have been looking at are 60A supplies (lots of margin),
90mV P-P ripple, and possibly an additional 1% or 2% after considering
tolerance, line regulation, and load regulation.
Rich -- I would also love to know what types of switching supplies you've
used on the KL. An existence proof is always extremely useful.
James Markevitch
The spec on the ripple is 20MHz and 100mV (or
1.0% pk-pk).
The 100mV would be no problem for TTL, NMOS, or CMOS, and it would probably
be fine for a single-Vee-supply ECL system, but it is very high for a
multi-supply system. 10K MECL has worst-case noise margin for logic 1 of
only 82mV (Motorola MECL System Design Handbook Fourth Edition, HB205/D,
May 1988, chapter 5: Power Distribution). That worst-case analysis is
based on an output of a part at Vee(max) and an input of a part at
Vee(min). That's exactly the condition you will have for signals crossing
from one power supply domain into another, if the noise happens to be out
of phase. IIRC there's not too much decoupling capacitance on the boards,
since they didn't need it. I'm not sure how much of that 1% pk-pk noise to
actually expect at the Vee pins of the chips.