30 Aug
2006
30 Aug
'06
8:03 p.m.
Brad Parker wrote:
Don North wrote:
The 'original' use for DATIP-DATO (vs a sequence of DATI, DATO) was to
let core memory know it did not have to do the read-restore cycle, since
a DATO was coming right away to the exact same location and would
overwrite with new data. The memory could then be a little bit faster.
With MOS memory this is not necessary.
Some later CPUs (11/74) iirc altered all the 'normal' memory accesses to
be just DATI and DATO(B) cycles, and implemented the special sequence
DATIP-DATOB for the ASRB instruction to act as the atomic memory
interlock. But I digress...
Don
On all the discrete logic 11s and LSI11 the CLR
instr does a
...
thanks!
So if your hardware can't tolerate a read
access to a register, then you
can do a MOV #0,ADR instead of CLR ADR (and make a note in your code why
so some poor soul 30 years from now understands why you are doing a
non-optimal MOV #0,xxx!)
I fixed the hardware :-) I was just curious about which machines did
what.
The problem was that the two transactions are back to back and the bus
master keeps overnership. I was waiting for BBSY to go away...
-brad