16 Nov
2011
16 Nov
'11
11:31 a.m.
On 11/16/2011 1:15 PM, Chuck Guzis wrote:
This and Tony's comment about using discrete logic
rather than FPGA
points up an interesting, but important, limitation of FPGAs (and
CPLDs): they're clocked designs.
Chuck: This really isn't true at all. While you are right that most
designs are synchronous, there's no limitation or requirement for them
to be so. You can do combinatorial logic all day without a clock.
module AOI (input A, B, C, D, output F);
assign F = ~((A & B) | (C & D));
endmodule
is an example.
module MUX2 (input SEL, A, B, output F);
input SEL, A, B;
output F;
INV G1 (SEL, SELB);
AOI G2 (SELB, A, SEL, B, FB);
INV G3 (.A(FB), .F(F));
endmodule
I've also simulated these, and it appears to work fine. Maybe in larger
more complex designs, there's problems with simulations --- others here
will have to testify to that.
Am I missing something here? Why doesn't combinatorial logic designed in
an FPGA count as a clockless design?
Thanks
Keith