11 Nov
2012
11 Nov
'12
4:42 p.m.
On 10/4/2012 9:27 PM, Eric Smith wrote:
Rob Doyle wrote:
I'm still trying to understand the KS10 paging.
The KS10 hardware supports a 20-bit VMA but no sections - which
/should/ allow 1 MW memory.
Apparently ADP had modifications to implement 1 MW of memory.
Was the 512 KW memory limitation just a implementation limitation:
8 slots with 64 KW per slot? Or more than that?
Did the ADP KS10s run unmodified versions of the OSs?
Thanks.
Rob.
The KS10 FPGA is running well enough to execute (and fail) the
DEC Instruction Set Diagnostics. Each day it runs some more
instructions before halting.
What exactly are the architectural differences
between a KS and
KL?
The KL10 came in two versions, referred to as "Model A" and "Model
B".[*]
The difference is that the Model A supports the traditional 256KW
user address space, as was found on the earlier KI10 and KS10. The
Model B adds the concept of "sections", which adds another 12 bits to
the logical address, although the KL10 Model B only implements 5 of
them, for a maximum of 32 sections. This expands the user address
space to 8 Mwords.
Multiple section support involves changes to the way paging works,
introducing an additional level of tables. It also adds
complications to indirect words, byte pointers, and the PXCT
instruction, among other things.
The KS10 does not support multiple sections. Its data paths were
not designed for it, so there is no efficient way to add multiple
section support merely by adding microcode. From a non-system
programmer's perspective, the KS10 is similar to a KL10 Model A.