16 Nov
2011
16 Nov
'11
7:52 p.m.
Chuck Guzis wrote:
The few times I've tried to instantiate (right word? HDL-to-
implementation) a purely async design, the EDA tools pitch about
there being no clock signal.
Maybe I'm not RTFM, but I don't think so.
What happens if you try to, say, define a clock signal, assign the pins
to it, cable it up to a crystal, and then never connect it to any logic?
I mean, yeah, you'd be out a couple of pins, but does it work?
Peace... Sridhar
This and Tony's comment about using discrete logic
rather than FPGA
points up an interesting, but important, limitation of FPGAs (and
CPLDs): they're clocked designs.
Chuck: This really isn't true at all. While you are right that most
designs are synchronous, there's no limitation or requirement for them
to be so. You can do combinatorial logic all day without a clock.
module AOI (input A, B, C, D, output F);
assign F = ~((A& B) | (C& D));
endmodule