16 Nov
2011
16 Nov
'11
9:04 p.m.
I wrote:
I've done a limited amount of asynchronous logic
in Spartan-3
FPGAs.
Chuck Guzis wrote:
Do you think you'd have any trouble working up an
implementation of
this 19-year old design in FPGA?
http://brendaluderman.info/cv/papers/An_Asynchronous_Multiplier.pdf
As an assignment for a class I took at San Jose State a few years back,
I had to write a Verilog description of a 4x4 array multiplier,
synthesize it for an XC3S200, and test it on a Spartan 3 starter kit.
Extending it to 32-bit would be trivial. The only reason it was 4x4
instead of some larger size is that the board had eight slide switches
for input.
It wasn't self-timed, though. In other words, I didn't have the
"Control Block" with REQ, ACK, and Carry Completion signals described in
the paper. I don't think it would be too difficult to implement that.