17 Nov
2011
17 Nov
'11
5:39 a.m.
On Nov 16, 2011, at 10:28 PM, Chuck Guzis wrote:
On 16 Nov 2011 at 18:44, Eric Smith wrote:
You could do that. I've only skimmed the paper, so I can't say for sure if it
does, but if it requires specific timing relationships between any of the asynchronous
parts (e.g. X arrives later than Y), you might find it a little hard without setting lots
of timing constraints on individual nets.
The main reason for that is that while each LUT and flip-flop will have a basically
identical propagation delay, the implementation tool will decide where they go on the die.
Obviously, different routing lengths make a pretty big difference (even more so in
silicon than on a board; sometimes on the order of several ns).
I might give it a shot and see what comes out when I've got some spare time.
- Dave
> I've done a limited amount of
asynchronous logic in Spartan-3
FPGAs.
Xilinx says don't do it, and the static
timing analysis tool throws up
its hands, but with a little effort it seems possible to do it.
However, I wouldn't want the job of implementing a large async circuit
in an FPGA. Life's too short.
Do you think you'd have any trouble working up an implementation of
this 19-year old design in FPGA?
http://brendaluderman.info/cv/papers/An_Asynchronous_Multiplier.pdf
Nothing big, say 32x32 bit.
I'm just trying to figure out how far this FPGA thing can be pushed.