26 Apr
2013
26 Apr
'13
6:52 a.m.
On Apr 26, 2013, at 1:34 AM, alan at alanlee.org wrote:
I don't get your objection or what you see as an alternative to modern FPGA
vendors. FPGA hardware is well documented by all 4 major vendors at a cell,
routing, and overall architecture level. Pick up a family handbook from one of
them and I think you'll be shocked at just how much gory detail is actually in
there - detailed almost down to a gate level. HDLs isolate you from having to
deal with manually connecting gate A to gate B times thousands of nets in a
relatively portable way.
Mouse's objection is based on the fact that they don't document the
functions of the configuration bitstream, without which you cannot write
your own synthesis software. In the case of things like PALs and GALs,
the datasheets for the device specify what each bit in the bitstream does
as far as turning on minterms, inverting outputs, etc. The programming
algorithms for GALs at least are proprietary (I think), but they have
been reverse engineered fairly well.
I don't really disagree; I think the bitstream functionality (note: this
is distinct from the FORMAT of the bitstream, which Xilinx discloses
without describing what the actual config bits do) should be open so that
people can do more interesting things with the FPGAs. The fact that it
is not does not stop me from using them, though, because I do not have as
many serious reservations about using closed, proprietary software.
I can't imagine you being an MPU/MCU fan as ABI
licencors like ARM, MIPS, Intel,
Freescale, etc don't open source the gate level designs for 99% of the worlds
most popular CPUs either. FPGA are way more open and more documented in that
regard as you can instance your own designed CPU or a dozen open ones across
thousands of programmable devices both past and well into the future. And once
you prototype your own design, many FPGA vendors have ASIC services where you
can mask your chip in hard silicon then it really will be your own design you
can open source if you desire.
The difference here is that CPU vendors don't have proprietary, hidden
instruction sets (let's ignore undocumented diagnostic instructions for
the moment). If you had a CPU that required you to use a proprietary
compiler that generated code that you were contractually prohibited
from disassembling, you might think twice about using
that CPU instead
of one of the many others with an otherwise open architecture
(I'm not
talking about the masks, I'm talking about what you run on it). Sadly,
there are no FPGAs that I am aware of that are open alternatives to the
status quo.
Tools from Xilinx, Altera, Lattice, and MicroSemi run
on Linux as well as
Windows.
Mouse does not run Linux or Windows or x86 processors, to my knowledge.
Xilinx and Altera both used to run on Solaris and HP-UX for Sparc and
HP-PA, respectively, but those were discontinued many years ago. For
modern FPGAs, you really need to be running pretty beefy, modern iron
to compile in any sort of reasonable timeframe. My 8-core Xeon with
8 GB of RAM takes 45 minutes to compile even a medium-sized Arria II
(Altera's mid-level FPGA) that's half-full, so I don't think a
SparcStation 20 would be an ideal candidate for running the exhaustive
search algorithms necessary for building modern devices, but if you
were able to write your own generation software, you could at least
route it yourself (with all the hazards that entails).
- Dave