1 Sep
2014
1 Sep
'14
7:42 p.m.
On 2014-Sep-01, at 5:41 PM, drlegendre . wrote:
Just noticed some errors in the CCS DRAM board
schematic. Both U4 (74LS20)
and U5 (7400) are drawn as an OR gates. I'm sure there's more..
No they're not drawn incorrectly, they are drawn in their negative-logic formulation.
Think through the logic states of the inputs as they are drawn and you'll find
it's the same as the NAND gates you expect.
This is done to represent the functional intention of the logic design, which sometimes
doesn't mesh with the 'standard' (positive-logic) presentation.
U7 to the right however, actually is drawn incorrectly. It's a NOR gate, but the
intention is that of an AND gate with inverted inputs, except they forgot to draw the
inversion bubbles on the inputs.
On 2014-Sep-01, at 6:06 PM, drlegendre . wrote:
Sorry for the trickle, here, but I'm making
progress and need to keep
things rolling.
So OK, I think I understand how the board enable/disable circuits work, now
that Brent tipped me off to U4. The output of U4 runs to one input of the
3-input NAND at U3. PHANTOM also comes in on U3, as does another signal
from the output of U7 I don't know. Point is, so long as all of these 3
remain high, the output of U3 remains low. If any of the 3 go low, output
of U3 goes high.
The output of U3 ties to the (overlined) OE (output enable?) of U20.. which
is a tri-state device. So if that input were to go high, then the outputs
of U20 all go high-Z and effectively cut-off lines DI0-DI7 to the RAM
matrix. I think DI=Data In, right? So in other words, if any of the 3
inputs to U3 goes low, the DI0-DI7 lines go high-Z and cutoff from the
buss..
Did I get that right?
Yes.
And stated in the complement, all three inputs to U3 must be high for the mem board to put
data on the bus.
The third input (U7 from discussion above) is a combination of nMEMR and PDBIN, MEMR
indicates this is a memory read cycle, PDBIN is a strobe telling the mem board it can put
the data onto the bus now (while the strobe is active).