16 Nov
2011
16 Nov
'11
9:03 p.m.
On 11/16/2011 10:28 PM, Chuck Guzis wrote:
On 16 Nov 2011 at 18:44, Eric Smith wrote:
Chuck,
While I'm not sure about the async multiplier you link to on that paper,
for what it's worth, there is an async 32x32-bit multiplier here
http://pastebin.com/NqtpNuDz
My $150-ish eval board with the Xilinx Spartan-3e contains (20)
dedicated 18 bit signed x 18 bit signed multipliers, this design uses
four of them.
My math skills are pretty weak, but they basically split the 32-bit
operands (a,b in this case) into 16-bit chunks, append binary 00 to them
to have 18-bit chunks, feed them into the multipliers, and then smash
the results together.
Most of the code is just dealing with the fact that the inputs to the
multipliers have to be 18 bits chunks.....
The inputs are a,b,sign, with p as an output.
The on-die multipliers are doing all the work.
Not a clock in sight. :)
Hope this helps.
Keith
> I've done a limited amount of
asynchronous logic in Spartan-3
FPGAs.
Xilinx says don't do it, and the static
timing analysis tool throws up
its hands, but with a little effort it seems possible to do it.
However, I wouldn't want the job of implementing a large async circuit
in an FPGA. Life's too short.
Do you think you'd have any trouble working up an implementation of
this 19-year old design in FPGA?
http://brendaluderman.info/cv/papers/An_Asynchronous_Multiplier.pdf
Nothing big, say 32x32 bit.
I'm just trying to figure out how far this FPGA thing can be pushed.
--Chuck