25 Apr
2013
25 Apr
'13
8:49 p.m.
On Apr 25, 2013, at 6:41 PM, Sytse van Slooten wrote:
The other thing that helped me a lot is that with the
behavioral languages you
should always have in the back of your mind some image of how it will
translate to hardware - ie, not think like 'if this happens, then it will do
that' but rather 'the if will cause a comparator to be made, which feeds an
enable signal towards X'.
Schematic capture can take you a long way, but it's much more 'hardware
style'
work than VHDL or Verilog. I initially thought I would like schematic capture
a lot better, but after a couple of days of drawing, I changed my mind. The
initial setup is fairly doable, but changing your design can be a headache
with schematics. I think Altera's Quartus still lets you do schematics, but
I'm not so sure about Xilinx' ISE.
Two crucial things about doing FPGA design in schematic capture, aside
from what you've already mentioned:
1) The schematic capture tools are not portable across vendors. Altera
and Xilinx do not cross-import each others' schematics. You can do
schematic entry in Altium Designer and export it to Altera and Xilinx
projects, but that's a really silly thing to do.
2) FPGAs use lookup tables to essentially implement the truth tables of
logical functions, not individual AND and OR gates (or product terms,
like real CPLDs and PALs and PLAs and other early programmable logic
devices do). Modern FPGAs use a MINIMUM of four-input LUTs, and the
trend with newer ones is 6-input (or Altera's ALM "fracturable 8-input
LUT" structure, which is kind of weird but also really flexible and
lets you do things like crossbar switches with way fewer resources).
When you design at the schematic capture level, as Sytse mentioned,
you tend to lose a sense of that. Things that look like a mess of
AND, OR, NOT and XOR gates can turn into a single LUT rather easily,
which is a lot easier to see when you're doing it at the HDL level.
Also, things like adders for which there is architectural acceleration
available (like hardware carry chains, sometimes even full adders
built into the logic element) aren't going to get used if you're e.g.
building your ALU out of raw gates.
When we see any of our customers doing FPGA design by schematic entry,
it's usually a sign that something is dreadfully wrong with their
engineering department, because it's akin to trying to build a rocket
out of bubble gum and paperclips (at least with what modern FPGAs are
purposed for). Just don't do it. Learn Verilog or VHDL, or better
yet both. They will take you far.
- Dave