DEC KS-10 FPGA

I've starting to create a DEC KS10 (PDP-10) in an FPGA. I've done some rapid prototyping as a proof-of-concept just to judge the quality of the documentation and to get a rough idea about the size of the task. I've got an ALU, microsequencer, Control ROM microcode, Dispatch ROM microcode, dispatch logic, skip logic, AC register, XR register, IR register, and the bus multiplexers all roughed in. It works well enough to execute the first half-dozen microinstructions correctly - maybe more. My goal is to implement the hardware close enough to run the microcode unchanged. When that is working well enough, we can add TTY IO and a disk controller. Because the KS10 only implemented half of it's microcode address space, we have plenty of unused address space to add microcode support for the on-board peripherals. If anybody is interested in collaborating, learning Verilog and/or FPGA design, goofing around, or participating in any way, please let me know off-list. Rob. doyle at cox dot net