16 Nov
2011
16 Nov
'11
12:47 p.m.
On 16 Nov 2011 at 14:31, Keith Monahan wrote:
On 11/16/2011 1:15 PM, Chuck Guzis wrote:
The few times I've tried to instantiate (right word? HDL-to-
implementation) a purely async design, the EDA tools pitch about
there being no clock signal.
Maybe I'm not RTFM, but I don't think so.
--Chuck
This and Tony's comment about using discrete
logic rather than FPGA
points up an interesting, but important, limitation of FPGAs (and
CPLDs): they're clocked designs.
Chuck: This really isn't true at all. While you are right that most
designs are synchronous, there's no limitation or requirement for them
to be so. You can do combinatorial logic all day without a clock.
module AOI (input A, B, C, D, output F);
assign F = ~((A & B) | (C & D));
endmodule