31 Jul
2000
31 Jul
'00
12:56 p.m.
The most common uses of VHDL seem to be somewhere
inbetween. Pure
behavioral descriptions are fine for simulation but don't tend to work
well for synthesis, so large designs are usually built as structural
descriptions of smaller behavioral subdesigns.
It seems that VHDL (and Verilog) has moved 99.9 percent away from its
original purpose, that of pure documentation (I wonder if the original
designers ever thought the language would be used for non-military
development?). It also seems that the original need for VHDL has only
been used a few times (which is actually the way it is supposed to be.).
William Donzelli
aw288(a)osfn.org