on FPGA simulation

On Nov 16, 2011, at 2:23 PM, Mouse wrote: To be fair, it's not just their tools; it's everyone's tools. Every FPGA vendor I know has hooks to use third-party synthesis engines (such as the big ones also used to design ASICs); the FPGA tools then perform the job of translating their netlists to the device-specific elements and from there into a bitstream. The third-party synthesis tools don't do a lot of timing analysis themselves (that's generally hard to do without knowledge of the underlying hardware), but they often expect synchronous designs. FPGA toolkits will give you pin-to-pin propagation delays when it's appropriate. The CPLD tools are usually better about making that data more apparent, because real CPLDs are fairly register-poor and people do lots of combinational things with them (address decoding and the like). Such data is present in the output reports of the FPGA engines too, but since they assume most people aren't doing that, there's no fancy synopsis export for that. You generally need to grep the very very long timing report. - Dave