16 Nov
2011
16 Nov
'11
10:15 a.m.
On 15 Nov 2011 at 20:40, Keith Monahan wrote:
FWIW, I love simulation with FPGAs. It usually
reveals my beginner
mistakes, and is a pretty powerful tool to help test your design.
While I haven't done enough to demonstrate it, there are differences
between simulation and real hardware.
This and Tony's comment about using discrete logic rather than FPGA
points up an interesting, but important, limitation of FPGAs (and
CPLDs): they're clocked designs.
While Tony can use his 7400-series logic to implement an asynchronous
design, almost all FPGA implementations must have a clock of some
sort.
Not every design employing logic is a CPU and not all employ clocked
logic.
Someone who wants to substitute, say, a CPLD for a bunch of unclocked
TTL is going to have to come up with a clock--and then determine how
that will affect function.
Achronix is the only vendor that I can recall offhand even discussing
aysnchronous FPGAs--and it's not even clear to me if they're still
offering them. Simulation must be a nightmare.
--Chuck