31 Jul
2006
31 Jul
'06
10:01 a.m.
On Mon, 31 Jul 2006, Pierre-Marie BOYER wrote:
Le Dimanche 30 Juillet 2006 18:19, jim stephens a
?crit?:
If your ADC runs at 30 MHz, could DRAM refresh could be turned off for the
duration of the data aquisition cycle? (30 MHz ought to be fast enough to do
all the rows in the refresh period)
Probably requires some perusal of the SDRAM/SDRAM controller data sheet to see
if this is feasble. Also may not work if you have multiple physical RAM banks
(got to refresh the other banks somehow)
Peter Wallace
Pierre-Marie BOYER wrote:
No, ADC data run at a fixed frequency (30 MHz) during several seconds,
so data, from the ADC, must be writen to the sdram at rate one byte every 0,03 usec,
during several seconds.
( ADC hasn't buffer).
But what happend when the SDRAM enter in its refresh cycle, which occurs every 64ms ?
Tanks
P.M.B.
Hi !
The ADC send data to the SDRAM through the DMA at a fixed rate during
may be 1 or 2 second, and is this process
can be stopped/disturbed by the internal refresh process of SDRAM ?
If yes, is there a solution, to manage the two process ( fixed
acquisition and SDRAM refresh cycle) ?
Thank you very much.
If you are only collecting ADC data at that rate, can you use an I/O mapped
device instead of DMA, and just poll and read the data? Or are you saying
that the ADC data will start up and run at some rate approaching the memory
cycle time for 1 to 2 seconds?